One embodiment of the invention relates to a control unit which is set up to generate and output periodic clock signals, which are in sync with and at the same frequency as a periodic basic clock which is input into it, and synchronous periodic control signals and to activate/deactivate output of at least the clock signals in reaction to an activation/deactivation signal supplied to it externally. This control unit can be used to control a parallel/serial converter, executing synchronization and serialization of a parallel data signal in sync with the basic clock, in the transmission interface circuit for fast DDR-DRAM memories in future memory generations and/or for a memory controller actuating said memories.
Future DDR-DRAM memory generations will have very high transmission frequencies and will be subjected to various limitations: the transmission interface circuit of such future DDR-DRAM memories will firstly need to have low power consumption and will secondly need to be able to output the data at the demanded high frequencies.
For this purpose, a control unit for generating the clock and control signals required in the transmission interface circuit is desired which can turn off said signals when no data are being transmitted.